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| triple-channel digital isolators adum1300/adum1301 rev. h information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2003C2008 analog devices, inc. all rights reserved. features automotive versions qualified per aec-q100 low power operation 5 v operation 1.2 ma per channel maximum @ 0 mbps to 2 mbps 3.5 ma per channel maximum @ 10 mbps 32 ma per channel maximum @ 90 mbps 3 v operation 0.8 ma per channel maximum @ 0 mbps to 2 mbps 2.2 ma per channel maximum @ 10 mbps 20 ma per channel maximum @ 90 mbps bidirectional communication 3 v/5 v level translation high temperature operation: 125c high data rate: dc to 90 mbps (nrz) precise timing characteristics 2 ns maximum pulse width distortion 2 ns maximum channel-to-channel matching high common-mode transient immunity: >25 kv/s output enable function 16-lead soic wide body package rohs-compliant models available safety and regulatory approvals ul recognition: 2500 v rms for 1 minute per ul 1577 csa component acceptance notice #5a vde certificate of conformity din v vde v 0884-10 (vde v 0884-10):2006-12 v iorm = 560 v peak tv approval: iec/en/ul/csa 61010-1 applications general-purpose multichannel isolation spi interface/data converter isolation rs-232/rs-422/rs-485 transceivers industrial field bus isolation automotive systems general description the adum130x 1 are triple-channel digital isolators based on the analog devices, inc., i coupler? technology. combining high speed cmos and monolithic transformer technology, these isolation components provide outstanding performance characteristics superior to alternatives, such as optocouplers. by avoiding the use of leds and photodiodes, i coupler devices remove the design difficulties commonly associated with optocouplers. the typical optocoupler concerns regarding uncertain current transfer ratios, nonlinear transfer functions, and temperature and lifetime effects are eliminated with the simple i coupler digital interfaces and stable performance characteristics. the need for external drivers and other discrete components is eliminated with these i coupler products. furthermore, i coupler devices consume one-tenth to one-sixth of the power of optocouplers at comparable signal data rates. the adum130x isolators provide three independent isolation channels in a variety of channel configurations and data rates (see the ordering guide ). both models operate with the supply voltage on either side ranging from 2.7 v to 5.5 v, providing compatibility with lower voltage systems as well as enabling a voltage translation functionality across the isolation barrier. in addition, the adum130x provide low pulse width distortion (<2 ns for crw grade) and tight channel-to-channel matching (<2 ns for crw grade). unlike other optocoupler alternatives, the adum130x isolators have a patented refresh feature that ensures dc correctness in the absence of input logic transitions and when power is not applied to one of the supplies. 1 protected by u.s. patents 5,952, 849; 6,873,065; 6,903,578; and 7,075,329. other patents are pending. functional block diagrams encode decode encode decode encode decode v dd1 g nd 1 v ia v ib v ic nc nc g nd 1 v dd2 gnd 2 v oa v ob v oc nc v e2 gnd 2 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 03787-001 figure 1. adum1300 functional block diagram decode encode encode decode encode decode v dd1 gnd 1 v ia v ib v oc nc v e1 gnd 1 v dd2 gnd 2 v oa v ob v ic nc v e2 gnd 2 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 03787-002 figure 2. adum1301 functional block diagram
adum1300/adum1301 rev. h | page 2 of 28 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 functional block diagrams ............................................................. 1 revision history ............................................................................... 3 specifications ..................................................................................... 4 electrical characteristics5 v, 105c operation ................... 4 electrical characteristics3 v, 105c operation ................... 6 electrical characteristicsmixed 5 v/3 v or 3 v/5 v, 105c operation ....................................................................................... 8 electrical characteristics5 v, 125c operation ................. 11 electrical characteristics3 v, 125c operation ................. 13 electrical characteristicsmixed 5 v/3 v, 125c operation ..................................................................................... 15 electrical characteristicsmixed 3 v/5 v operation .......... 17 package characteristics ............................................................. 19 regulatory information ............................................................. 19 insulation and safety-related specifications .......................... 19 din v vde v 0884-10 (vde v 0884-10):2006-12 insulation characteristics ............................................................................ 20 recommended operating conditions .................................... 20 absolute maximum ratings ......................................................... 21 esd caution................................................................................ 21 pin configurations and function descriptions ......................... 22 typical performance characteristics ........................................... 23 applications information .............................................................. 25 pc board layout ........................................................................ 25 propagation delay-related parameters ................................... 25 dc correctness and magnetic field immunity ........................... 25 power consumption .................................................................. 26 insulation lifetime ..................................................................... 27 automotive products ................................................................. 27 outline dimensions ....................................................................... 28 ordering guide .......................................................................... 28 adum1300/adum1301 rev. h | page 3 of 28 revision history 5/08rev. g to rev. h added adum1300w and adum1301w parts ............. universal changes to features list ................................................................... 1 added table 4 .................................................................................. 11 added table 5 .................................................................................. 13 added table 6 .................................................................................. 15 added table 7 .................................................................................. 17 changes to table 12 ........................................................................ 20 changes to table 13 ........................................................................ 21 added automotive products section ........................................... 27 changes to ordering guide ........................................................... 28 11/07rev. f to rev. g changes to note 1 and figure 2 ...................................................... 1 added adum130xarw change vs. temperature parameter ... 3 added adum130xarw change vs. temperature parameter ... 5 added adum130xarw change vs. temperature parameter ... 8 changes to figure 14 ...................................................................... 16 6/07rev. e to rev. f updated vde certification throughout ....................................... 1 changes to features, note 1, figure 1, and figure 2 .................... 1 changes to regulatory information section ............................... 10 added table 10 ................................................................................ 12 added insulation lifetime section ............................................... 17 updated outline dimensions ........................................................ 19 changes to ordering guide ........................................................... 19 2/06rev. d to rev. e updated format .................................................................. universal added tv approval ....................................................... universal changes to figure 2 ........................................................................... 1 5/05rev. c to rev. d changes to format ............................................................. universal changes to figure 2 .......................................................................... 1 changes to table 6 .......................................................................... 10 changes to ordering guide ........................................................... 18 6/04rev. b to rev. c changes to format ............................................................. universal changes to features .......................................................................... 1 changes to electrical characteristics5 v operation ................ 3 changes to electrical characteristics3 v operation ................ 5 changes to electrical characteristicsmixed 5 v/3 v or 3 v/5 v operation ............................................................................ 7 changes to ordering guide ........................................................... 18 5/04rev. a to rev. b changes to the format ...................................................... universal changes to the features.................................................................... 1 changes to table 7 and table 8 ..................................................... 14 changes to table 9 .......................................................................... 15 changes to the dc correctness and magnetic field immunity section .............................................................................................. 19 changes to the power consumption section .............................. 20 changes to the ordering guide .................................................... 21 9/03rev. 0 to rev. a edits to regulatory information ................................................... 13 edits to absolute maximum ratings ............................................ 15 deleted the package branding information ................................ 16 9/03revision 0: initial version adum1300/adum1301 rev. h | page 4 of 28 specifications electrical characteristics5 v, 105c operation all voltages are relative to their respective ground. 4.5 v v dd1 5.5 v, 4.5 v v dd2 5.5 v; all minimum/maximum specifications apply over the entire recommended operation range, unless otherwise noted; all typical specifications are at t a = 25c, v dd1 = v dd2 = 5 v. these specifications do not apply to adum1300w and adum1301w automotive grade versions. table 1. parameter symbol min typ max unit test conditions dc specifications input supply current per channel, quiescent i ddi (q) 0.50 0.53 ma output supply current pe r channel, quiescent i ddo (q) 0.19 0.24 ma adum1300 total supply current three channels 1 dc to 2 mbps v dd1 supply current i dd1 (q) 1.6 2.5 ma dc to 1 mhz logic signal freq. v dd2 supply current i dd2 (q) 0.7 1.0 ma dc to 1 mhz logic signal freq. 10 mbps (brw and crw grades only) v dd1 supply current i dd1 (10) 6.5 8.1 ma 5 mhz logic signal freq. v dd2 supply current i dd2 (10) 1.9 2.5 ma 5 mhz logic signal freq. 90 mbps (crw grade only) v dd1 supply current i dd1 (90) 57 77 ma 45 mhz logic signal freq. v dd2 supply current i dd2 (90) 16 18 ma 45 mhz logic signal freq. adum1301 total supply current, three channels 1 dc to 2 mbps v dd1 supply current i dd1 (q) 1.3 2.1 ma dc to 1 mhz logic signal freq. v dd2 supply current i dd2 (q) 1.0 1.4 ma dc to 1 mhz logic signal freq. 10 mbps (brw and crw grades only) v dd1 supply current i dd1 (10) 5.0 6.2 ma 5 mhz logic signal freq. v dd2 supply current i dd2 (10) 3.4 4.2 ma 5 mhz logic signal freq. 90 mbps (crw grade only) v dd1 supply current i dd1 (90) 43 57 ma 45 mhz logic signal freq. v dd2 supply current i dd2 (90) 29 37 ma 45 mhz logic signal freq. for all models input currents i ia , i ib , i ic , i e1 , i e2 ?10 +0.01 +10 a 0 v v ia , v ib , v ic v dd1 or v dd2 , 0 v v e1 , v e2 v dd1 or v dd2 logic high input threshold v ih , v eh 2.0 v logic low input threshold v il , v el 0.8 v logic high output voltages v oah , v obh , v och (v dd1 or v dd2 ) ? 0.1 5.0 v i ox = ?20 a, v ix = v ixh (v dd1 or v dd2 ) ? 0.4 4.8 v i ox = ?4 ma, v ix = v ixh logic low output voltages v oal , v obl , v ocl 0.0 0.1 v i ox = 20 a, v ix = v ixl 0.04 0.1 v i ox = 400 a, v ix = v ixl 0.2 0.4 v i ox = 4 ma, v ix = v ixl switching specifications adum130xarw minimum pulse width 2 pw 1000 ns c l = 15 pf, cmos signal levels maximum data rate 3 1 mbps c l = 15 pf, cmos signal levels propagation delay 4 t phl , t plh 50 65 100 ns c l = 15 pf, cmos signal levels pulse width distortion, |t plh ? t phl | 4 pwd 40 ns c l = 15 pf, cmos signal levels change vs. temperature 11 ps/c c l = 15 pf, cmos signal levels propagation delay skew 5 t psk 50 ns c l = 15 pf, cmos signal levels channel-to-channel matching 6 t pskcd /t pskod 50 ns c l = 15 pf, cmos signal levels adum1300/adum1301 rev. h | page 5 of 28 parameter symbol min typ max unit test conditions adum130xbrw minimum pulse width 2 pw 100 ns c l = 15 pf, cmos signal levels maximum data rate 3 10 mbps c l = 15 pf, cmos signal levels propagation delay 4 t phl , t plh 20 32 50 ns c l = 15 pf, cmos signal levels pulse width distortion, |t plh ? t phl | 4 pwd 3 ns c l = 15 pf, cmos signal levels change vs. temperature 5 ps/c c l = 15 pf, cmos signal levels propagation delay skew 5 t psk 15 ns c l = 15 pf, cmos signal levels channel-to-channel matching, codirectional channels 6 t pskcd 3 ns c l = 15 pf, cmos signal levels channel-to-channel matching, opposing- directional channels 6 t pskod 6 ns c l = 15 pf, cmos signal levels adum130xcrw minimum pulse width 2 pw 8.3 11.1 ns c l = 15 pf, cmos signal levels maximum data rate 3 90 120 mbps c l = 15 pf, cmos signal levels propagation delay 4 t phl , t plh 18 27 32 ns c l = 15 pf, cmos signal levels pulse width distortion, |t plh ? t phl | 4 pwd 0.5 2 ns c l = 15 pf, cmos signal levels change vs. temperature 3 ps/c c l = 15 pf, cmos signal levels propagation delay skew 5 t psk 10 ns c l = 15 pf, cmos signal levels channel-to-channel matching, codirectional channels 6 t pskcd 2 ns c l = 15 pf, cmos signal levels channel-to-channel matching, opposing- directional channels 6 t pskod 5 ns c l = 15 pf, cmos signal levels for all models output disable propagation delay (high/low to high impedance) t phz , t plh 6 8 ns c l = 15 pf, cmos signal levels output enable propagation delay (high impedance to high/low) t pzh , t pzl 6 8 ns c l = 15 pf, cmos signal levels output rise/fall time (10% to 90%) t r /t f 2.5 ns c l = 15 pf, cmos signal levels common-mode transient immunity at logic high output 7 |cm h | 25 35 kv/s v ix = v dd1 or v dd2 , v cm = 1000 v, transient magnitude = 800 v common-mode transient immunity at logic low output 7 |cm l | 25 35 kv/s v ix = 0 v, v cm = 1000 v, transient magnitude = 800 v refresh rate f r 1.2 mbps input dynamic supply current per channel 8 i ddi (d) 0.19 ma/mbps output dynamic supply current per channel 8 i ddo (d) 0.05 ma/mbps 1 the supply current values are for all three channels combined when runni ng at identical data rate s. output supply current valu es are specified with no output load present. the supply current associat ed with an individual channel op erating at a given data rate may be calculated as described in the section. see through for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. see f through for total v dd1 and v dd2 supply currents as a function of data rate for adum1300/adum1301 ch annel configurations. power consumption power consumption figure 6 fig ure 6 figure 8 figure 8 igure 9 figure 12 2 the minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed. 3 the maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed. 4 t phl propagation delay is measured from the 50% level of the falling edge of the v ix signal to the 50% level of the falling edge of the v ox signal. t plh propagation delay is measured from the 50% level of the rising edge of the v ix signal to the 50% level of the rising edge of the v ox signal. 5 t psk is the magnitude of the worst-case difference in t phl or t plh that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. 6 codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channe ls with inputs on the same side of the isolation barrier. opposi ng-directional channe l-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier. 7 cm h is the maximum common-mode voltage slew rate that can be sustained while maintaining v o > 0.8 v dd2 . cm l is the maximum common-mod e voltage slew rate that can be sustained while maintaining v o < 0.8 v. the common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. the transient magnitude is the range over which the common mode is slewed. 8 dynamic supply current is the incremental amou nt of supply current required for a 1 mbps increase in signal data rate. see through for information on per-channel supply current for unloaded and loaded conditions. see the section for guidance on calculating the per-channel supply current for a given data rate. adum1300/adum1301 rev. h | page 6 of 28 electrical characteristics3 v, 105c operation all voltages are relative to their respective ground. 2.7 v v dd1 3.6 v, 2.7 v v dd2 3.6 v; all minimum/maximum specifications apply over the entire recommended operation range, unless otherwise noted; all typical specifications are at t a = 25c, v dd1 = v dd2 = 3.0 v. these specifications do not apply to adum1300w and adum1301w automotive grade versions. table 2. parameter symbol min typ max unit test conditions dc specifications input supply current per channel, quiescent i ddi (q) 0.26 0.31 ma output supply current pe r channel, quiescent i ddo (q) 0.11 0.15 ma adum1300 total supply current, three channels 1 dc to 2 mbps v dd1 supply current i dd1 (q) 0.9 1.7 ma dc to 1 mhz logic signal freq. v dd2 supply current i dd2 (q) 0.4 0.7 ma dc to 1 mhz logic signal freq. 10 mbps (brw and crw grades only) v dd1 supply current i dd1 (10) 3.4 4.9 ma 5 mhz logic signal freq. v dd2 supply current i dd2 (10) 1.1 1.6 ma 5 mhz logic signal freq. 90 mbps (crw grade only) v dd1 supply current i dd1 (90) 31 48 ma 45 mhz logic signal freq. v dd2 supply current i dd2 (90) 8 13 ma 45 mhz logic signal freq. adum1301 total supply current, three channels 1 dc to 2 mbps v dd1 supply current i dd1 (q) 0.7 1.4 ma dc to 1 mhz logic signal freq. v dd2 supply current i dd2 (q) 0.6 0.9 ma dc to 1 mhz logic signal freq. 10 mbps (brw and crw grades only) v dd1 supply current i dd1 (10) 2.6 3.7 ma 5 mhz logic signal freq. v dd2 supply current i dd2 (10) 1.8 2.5 ma 5 mhz logic signal freq. 90 mbps (crw grade only) v dd1 supply current i dd1 (90) 24 36 ma 45 mhz logic signal freq. v dd2 supply current i dd2 (90) 16 23 ma 45 mhz logic signal freq. for all models input currents i ia , i ib , i ic , i e1 , i e2 ?10 +0.01 +10 a 0 v v ia , v ib , v ic v dd1 or v dd2 , 0 v v e1 , v e2 v dd1 or v dd2 logic high input threshold v ih , v eh 1.6 v logic low input threshold v il , v el 0.4 v logic high output voltages v oah , v obh , v och (v dd1 or v dd2 ) ? 0.1 3.0 v i ox = ?20 a, v ix = v ixh (v dd1 or v dd2 ) ? 0.4 2.8 v i ox = ?4 ma, v ix = v ixh logic low output voltages v oal , v obl , v ocl 0.0 0.1 v i ox = 20 a, v ix = v ixl 0.04 0.1 v i ox = 400 a, v ix = v ixl 0.2 0.4 v i ox = 4 ma, v ix = v ixl switching specifications adum130xarw minimum pulse width 2 pw 1000 ns c l = 15 pf, cmos signal levels maximum data rate 3 1 mbps c l = 15 pf, cmos signal levels propagation delay 4 t phl , t plh 50 75 100 ns c l = 15 pf, cmos signal levels pulse width distortion, |t plh ? t phl | 4 pwd 40 ns c l = 15 pf, cmos signal levels change vs. temperature 11 ps/c c l = 15 pf, cmos signal levels propagation delay skew 5 t psk 50 ns c l = 15 pf, cmos signal levels channel-to-channel matching 6 t pskcd /t pskod 50 ns c l = 15 pf, cmos signal levels adum1300/adum1301 rev. h | page 7 of 28 parameter symbol min typ max unit test conditions adum130xbrw minimum pulse width 2 pw 100 ns c l = 15 pf, cmos signal levels maximum data rate 3 10 mbps c l = 15 pf, cmos signal levels propagation delay 4 t phl , t plh 20 38 50 ns c l = 15 pf, cmos signal levels pulse width distortion, |t plh ? t phl | 4 pwd 3 ns c l = 15 pf, cmos signal levels change vs. temperature 5 ps/c c l = 15 pf, cmos signal levels propagation delay skew 5 t psk 26 ns c l = 15 pf, cmos signal levels channel-to-channel matching, codirectional channels 6 t pskcd 3 ns c l = 15 pf, cmos signal levels channel-to-channel matching, opposing- directional channels 6 t pskod 6 ns c l = 15 pf, cmos signal levels adum130xcrw minimum pulse width 2 pw 8.3 11.1 ns c l = 15 pf, cmos signal levels maximum data rate 3 90 120 mbps c l = 15 pf, cmos signal levels propagation delay 4 t phl , t plh 20 34 45 ns c l = 15 pf, cmos signal levels pulse width distortion, |t plh ? t phl | 4 pwd 0.5 2 ns c l = 15 pf, cmos signal levels change vs. temperature 3 ps/c c l = 15 pf, cmos signal levels propagation delay skew 5 t psk 16 ns c l = 15 pf, cmos signal levels channel-to-channel matching, codirectional channels 6 t pskcd 2 ns c l = 15 pf, cmos signal levels channel-to-channel matching, opposing- directional channels 6 t pskod 5 ns c l = 15 pf, cmos signal levels for all models output disable propagation delay (high/low to high impedance) t phz , t plh 6 8 ns c l = 15 pf, cmos signal levels output enable propagation delay (high impedance to high/low) t pzh , t pzl 6 8 ns c l = 15 pf, cmos signal levels output rise/fall time (10% to 90%) t r /t f 3 ns c l = 15 pf, cmos signal levels common-mode transient immunity at logic high output 7 |cm h | 25 35 kv/s v ix = v dd1 or v dd2 , v cm = 1000 v, transient magnitude = 800 v common-mode transient immunity at logic low output 7 |cm l | 25 35 kv/s v ix = 0 v, v cm = 1000 v, transient magnitude = 800 v refresh rate f r 1.1 mbps input dynamic supply current per channel 8 i ddi (d) 0.10 ma/mbps output dynamic supply current per channel 8 i ddo (d) 0.03 ma/mbps 1 the supply current values are for all three channels combined when runni ng at identical data rate s. output supply current valu es are specified with no output load present. the supply current associat ed with an individual channel op erating at a given data rate may be calculated as described in the section. see through for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. see f through for total v dd1 and v dd2 supply currents as a function of data rate for adum1300/adum1301 ch annel configurations. power consumption power consumption figure 6 fig ure 6 figure 8 figure 8 igure 9 figure 12 2 the minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed. 3 the maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed. 4 t phl propagation delay is measured from the 50% level of the falling edge of the v ix signal to the 50% level of the falling edge of the v ox signal. t plh propagation delay is measured from the 50% level of the rising edge of the v ix signal to the 50% level of the rising edge of the v ox signal. 5 t psk is the magnitude of the worst-case difference in t phl or t plh that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. 6 codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channe ls with inputs on the same side of the isolation barrier. opposi ng-directional channe l-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier. 7 cm h is the maximum common-mode voltage slew rate that can be sustained while maintaining v o > 0.8 v dd2 . cm l is the maximum common-mod e voltage slew rate that can be sustained while maintaining v o < 0.8 v. the common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. the transient magnitude is the range over which the common mode is slewed. 8 dynamic supply current is the incremental amou nt of supply current required for a 1 mbps increase in signal data rate. see through for information on per-channel supply current for unloaded and loaded conditions. see the section for guidance on calculating the per-channel supply current for a given data rate. adum1300/adum1301 rev. h | page 8 of 28 electrical characteristicsmixed 5 v/3 v or 3 v/5 v, 105c operation all voltages are relative to their respective ground. 5 v/3 v operation: 4.5 v v dd1 5.5 v, 2.7 v v dd2 3.6 v; 3 v/5 v operation: 2.7 v v dd1 3.6 v, 4.5 v v dd2 5.5 v; all minimum/maximum specifications apply over the entire recommended operation range, unless otherwise noted; all typical specifications are at t a = 25c; v dd1 = 3.0 v, v dd2 = 5 v or v dd1 = 5 v, v dd2 = 3.0 v. these specifica- tions do not apply to adum1300w and adum1301w automotive grade versions. table 3. parameter symbol min typ max unit test conditions dc specifications input supply current per channel, quiescent i ddi (q) 5 v/3 v operation 0.50 0.53 ma 3 v/5 v operation 0.26 0.31 ma output supply current per channel, quiescent i ddo (q) 5 v/3 v operation 0.11 0.15 ma 3 v/5 v operation 0.19 0.24 ma adum1300 total supply current, three channels 1 dc to 2 mbps v dd1 supply current i dd1 (q) 5 v/3 v operation 1.6 2.5 ma dc to 1 mhz logic signal freq. 3 v/5 v operation 0.9 1.7 ma dc to 1 mhz logic signal freq. v dd2 supply current i dd2 (q) 5 v/3 v operation 0.4 0.7 ma dc to 1 mhz logic signal freq. 3 v/5 v operation 0.7 1.0 ma dc to 1 mhz logic signal freq. 10 mbps (brw and crw grades only) v dd1 supply current i dd1 (10) 5 v/3 v operation 6.5 8.1 ma 5 mhz logic signal freq. 3 v/5 v operation 3.4 4.9 ma 5 mhz logic signal freq. v dd2 supply current i dd2 (10) 5 v/3 v operation 1.1 1.6 ma 5 mhz logic signal freq. 3 v/5 v operation 1.9 2.5 ma 5 mhz logic signal freq. 90 mbps (crw grade only) v dd1 supply current i dd1 (90) 5 v/3 v operation 57 77 ma 45 mhz logic signal freq. 3 v/5 v operation 31 48 ma 45 mhz logic signal freq. v dd2 supply current i dd2 (90) 5 v/3 v operation 8 13 ma 45 mhz logic signal freq. 3 v/5 v operation 16 18 ma 45 mhz logic signal freq. adum1301 total supply current, three channels 1 dc to 2 mbps v dd1 supply current i dd1 (q) 5 v/3 v operation 1.3 2.1 ma dc to 1 mhz logic signal freq. 3 v/5 v operation 0.7 1.4 ma dc to 1 mhz logic signal freq. v dd2 supply current i dd2 (q) 5 v/3 v operation 0.6 0.9 ma dc to 1 mhz logic signal freq. 3 v/5 v operation 1.0 1.4 ma dc to 1 mhz logic signal freq. 10 mbps (brw and crw grades only) v dd1 supply current i dd1 (10) 5 v/3 v operation 5.0 6.2 ma 5 mhz logic signal freq. 3 v/5 v operation 2.6 3.7 ma 5 mhz logic signal freq. v dd2 supply current i dd2 (10) 5 v/3 v operation 1.8 2.5 ma 5 mhz logic signal freq. 3 v/5 v operation 3.4 4.2 ma 5 mhz logic signal freq. adum1300/adum1301 rev. h | page 9 of 28 parameter symbol min typ max unit test conditions 90 mbps (crw grade only) v dd1 supply current i dd1 (90) 5 v/3 v operation 43 57 ma 45 mhz logic signal freq. 3 v/5 v operation 24 36 ma 45 mhz logic signal freq. v dd2 supply current i dd2 (90) 5 v/3 v operation 16 23 ma 45 mhz logic signal freq. 3 v/5 v operation 29 37 ma 45 mhz logic signal freq. for all models input currents i ia , i ib , i ic , i e1 , i e2 ?10 +0.01 +10 a 0 v v ia , v ib , v ic v dd1 or v dd2 , 0 v v e1 , v e2 v dd1 or v dd2 logic high input threshold v ih , v eh 5 v/3 v operation 2.0 v 3 v/5 v operation 1.6 v logic low input threshold v il , v el 5 v/3 v operation 0.8 v 3 v/5 v operation 0.4 v logic high output voltages v oah , v obh , v och (v dd1 or v dd2 ) ? 0.1 (v dd1 or v dd2 ) v i ox = ?20 a, v ix = v ixh (v dd1 or v dd2 ) ? 0.4 (v dd1 or v dd2 ) ? 0.2 v i ox = ?4 ma, v ix = v ixh logic low output voltages v oal , v obl , v ocl 0.0 0.1 v i ox = 20 a, v ix = v ixl 0.04 0.1 v i ox = 400 a, v ix = v ixl 0.2 0.4 v i ox = 4 ma, v ix = v ixl switching specifications adum130xarw minimum pulse width 2 pw 1000 ns c l = 15 pf, cmos signal levels maximum data rate 3 1 mbps c l = 15 pf, cmos signal levels propagation delay 4 t phl , t plh 50 70 100 ns c l = 15 pf, cmos signal levels pulse width distortion, |t plh ? t phl | 4 pwd 40 ns c l = 15 pf, cmos signal levels change vs. temperature 11 ps/c c l = 15 pf, cmos signal levels propagation delay skew 5 t psk 50 ns c l = 15 pf, cmos signal levels channel-to-channel matching 6 t pskcd /t pskod 50 ns c l = 15 pf, cmos signal levels adum130xbrw minimum pulse width 2 pw 100 ns c l = 15 pf, cmos signal levels maximum data rate 3 10 mbps c l = 15 pf, cmos signal levels propagation delay 4 t phl , t plh 15 35 50 ns c l = 15 pf, cmos signal levels pulse width distortion, |t plh ? t phl | 4 pwd 3 ns c l = 15 pf, cmos signal levels change vs. temperature 5 ps/c c l = 15 pf, cmos signal levels propagation delay skew 5 t psk 6 ns c l = 15 pf, cmos signal levels channel-to-channel matching, codirectional channels 6 t pskcd 3 ns c l = 15 pf, cmos signal levels channel-to-channel matching, opposing- directional channels 6 t pskod 22 ns c l = 15 pf, cmos signal levels adum130xcrw minimum pulse width 2 pw 8.3 11.1 ns c l = 15 pf, cmos signal levels maximum data rate 3 90 120 mbps c l = 15 pf, cmos signal levels propagation delay 4 t phl , t plh 20 30 40 ns c l = 15 pf, cmos signal levels pulse width distortion, |t plh -t phl | 4 pwd 0.5 2 ns c l = 15 pf, cmos signal levels change vs. temperature 3 ps/c c l = 15 pf, cmos signal levels propagation delay skew 5 t psk 14 ns c l = 15 pf, cmos signal levels channel-to-channel matching, codirectional channels 6 t pskcd 2 ns c l = 15 pf, cmos signal levels channel-to-channel matching, opposing-directional channels 6 t pskod 5 ns c l = 15 pf, cmos signal levels adum1300/adum1301 rev. h | page 10 of 28 parameter symbol min typ max unit test conditions for all models output disable propagation delay (high/low to high impedance) t phz , t plh 6 8 ns c l = 15 pf, cmos signal levels output enable propagation delay (high impedance to high/low) t pzh , t pzl 6 8 ns c l = 15 pf, cmos signal levels output rise/fall time (10% to 90%) t r /t f c l = 15 pf, cmos signal levels 5 v/3 v operation 3.0 ns 3 v/5 v operation 2.5 ns common-mode transient immunity at logic high output 7 |cm h | 25 35 kv/s v ix = v dd1 or v dd2 , v cm = 1000 v transient magnitude = 800 v common-mode transient immunity at logic low output 7 |cm l | 25 35 kv/s v ix = 0 v, v cm = 1000 v, transient magnitude = 800 v refresh rate f r 5 v/3 v operation 1.2 mbps 3 v/5 v operation 1.1 mbps input dynamic supply current per channel 8 i ddi (d) 5 v/3 v operation 0.19 ma/mbps 3 v/5 v operation 0.10 ma/mbps output dynamic supply current per channel 8 i ddo (d) 5 v/3 v operation 0.03 ma/mbps 3 v/5 v operation 0.05 ma/mbps 1 the supply current values are for all three channels combined when running at identical data rates. output supply current valu es are specified with no output load present. the supply current associated with an individual channel operating at a given data rate may be calculated as described in the p section. see through for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. see through for total v dd1 and v dd2 supply currents as a function of data rate for adum1300/adum1301 channel configurations. ower consumption ower consumption figure 6 g ure 6 figure 8 figure 8 figur e 9 figure 12 2 the minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed. 3 the maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed. 4 t phl propagation delay is measured from the 50% level of the falling edge of the v ix signal to the 50% level of the falling edge of the v ox signal. t plh propagation delay is measured from the 50% level of the rising edge of the v ix signal to the 50% level of the rising edge of the v ox signal. 5 t psk is the magnitude of the worst-case difference in t phl or t plh that is measured between units at the same operating temperature, supply voltages , and output load within the recommended operating conditions. 6 codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channe ls with inputs on the same side of the isolation barrier. opposing-directional channel-to-channel matching is the ab solute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier. 7 cm h is the maximum common-mode voltage slew rate that can be sustained while maintaining v o > 0.8 v dd2 . cm l is the maximum common-mode voltage slew rate that can be sustained while maintaining v o < 0.8 v. the common-mode voltage slew rates apply to both rising and falling common-mode voltag e edges. the transient magnitud e is the range over which the common mode is slewed. 8 dynamic supply current is the incremental am ount of supply current required for a 1 mbps increase in signal data rate. see fi through for information on per-channel supply current for unloaded and loaded conditions. see the p section for guidance on calculating th e per-channel supply current for a given data rate. adum1300/adum1301 rev. h | page 11 of 28 electrical characteristics5 v, 125c operation all voltages are relative to their respective ground. 4.5 v v dd1 5.5 v, 4.5 v v dd2 5.5 v; all minimum/maximum specifications apply over the entire recommended operation range, unless otherwise noted; all typical specifications are at t a = 25c, v dd1 = v dd2 = 5 v. these specifications apply to adum1300w and adum1301w automotive grade versions. table 4. parameter symbol min typ max unit test conditions dc specifications input supply current per channel, quiescent i ddi (q) 0.50 0.53 ma output supply current per channel, quiescent i ddo (q) 0.19 0.24 ma adum1300w, total supply current three channels 1 dc to 2 mbps v dd1 supply current i dd1 (q) 1.6 2.5 ma dc to 1 mhz logic signal freq. v dd2 supply current i dd2 (q) 0.7 1.0 ma dc to 1 mhz logic signal freq. 10 mbps (trwz grade only) v dd1 supply current i dd1 (10) 6.5 8.1 ma 5 mhz logic signal freq. v dd2 supply current i dd2 (10) 1.9 2.5 ma 5 mhz logic signal freq. adum1301w, total supply current, three channels 1 dc to 2 mbps v dd1 supply current i dd1 (q) 1.3 2.1 ma dc to 1 mhz logic signal freq. v dd2 supply current i dd2 (q) 1.0 1.4 ma dc to 1 mhz logic signal freq. 10 mbps (trwz grade only) v dd1 supply current i dd1 (10) 5.0 6.2 ma 5 mhz logic signal freq. v dd2 supply current i dd2 (10) 3.4 4.2 ma 5 mhz logic signal freq. for all models input currents i ia , i ib , i ic , i e1 , i e2 ?10 +0.01 +10 a 0 v ia , v ib , v ic v dd1 or v dd2 , 0 v e1 , v e2 v dd1 or v dd2 logic high input threshold v ih , v eh 2.0 v logic low input threshold v il , v el 0.8 v logic high output voltages v oah , v obh , v och v dd1 , v dd2 ? 0.1 5.0 v i ox = ?20 a, v ix = v ixh v dd1 , v dd2 ? 0.4 4.8 v i ox = ?4 ma, v ix = v ixh logic low output voltages v oal , v obl , v ocl 0.0 0.1 v i ox = 20 a, v ix = v ixl 0.04 0.1 v i ox = 400 a, v ix = v ixl 0.2 0.4 v i ox = 4 ma, v ix = v ixl switching specifications adum130xwsrwz minimum pulse width 2 pw 1000 ns c l = 15 pf, cmos signal levels maximum data rate 3 1 mbps c l = 15 pf, cmos signal levels propagation delay 4 t phl , t plh 50 65 100 ns c l = 15 pf, cmos signal levels pulse width distortion, |t plh ? t phl | 4 pwd 40 ns c l = 15 pf, cmos signal levels propagation delay skew 5 t psk 50 ns c l = 15 pf, cmos signal levels channel-to-channel matching 6 t pskcd /t pskod 50 ns c l = 15 pf, cmos signal levels adum130xwtrwz minimum pulse width 2 pw 100 ns c l = 15 pf, cmos signal levels maximum data rate 3 10 mbps c l = 15 pf, cmos signal levels propagation delay 4 t phl , t plh 18 27 32 ns c l = 15 pf, cmos signal levels pulse width distortion, |t plh ? t phl | 4 pwd 3 ns c l = 15 pf, cmos signal levels change vs. temperature 5 ps/c c l = 15 pf, cmos signal levels propagation delay skew 5 t psk 15 ns c l = 15 pf, cmos signal levels channel-to-channel matching, codirectional channels 6 t pskcd 3 ns c l = 15 pf, cmos signal levels channel-to-channel matching, opposing- directional channels 6 t pskod 6 ns c l = 15 pf, cmos signal levels adum1300/adum1301 rev. h | page 12 of 28 parameter symbol min typ max unit test conditions for all models output disable propagation delay (high/low to high impedance) t phz , t plh 6 8 ns c l = 15 pf, cmos signal levels output enable propagation delay (high impedance to high/low) t pzh , t pzl 6 8 ns c l = 15 pf, cmos signal levels output rise/fall time (10% to 90%) t r /t f 2.5 ns c l = 15 pf, cmos signal levels common-mode transient immunity at logic high output 7 |cm h | 25 35 kv/s v ix = v dd1 /v dd2 , v cm = 1000 v, transient magnitude = 800 v common-mode transient immunity at logic low output 7 |cm l | 25 35 kv/s v ix = 0 v, v cm = 1000 v, transient magnitude = 800 v refresh rate f r 1.2 mbps input dynamic supply current per channel 8 i ddi (d) 0.19 ma/mbps output dynamic supply current per channel 8 i ddo (d) 0.05 ma/mbps 1 the supply current values are for all three channels combined when runni ng at identical data rate s. output supply current valu es are specified with no output load present. the supply current associat ed with an individual channel op erating at a given data rate may be calculated as described in the section. see through for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. see f through for total v dd1 and v dd2 supply currents as a function of data rate for adum1300w/adum1301w ch annel configurations. power consumption power consumption figure 6 fig ure 6 figure 8 figure 8 igure 9 figure 12 2 the minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed. 3 the maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed. 4 t phl propagation delay is measured from the 50% level of the falling edge of the v ix signal to the 50% level of the falling edge of the v ox signal. t plh propagation delay is measured from the 50% level of the rising edge of the v ix signal to the 50% level of the rising edge of the v ox signal. 5 t psk is the magnitude of the worst-case difference in t phl or t plh that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. 6 codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channe ls with inputs on the same side of the isolation barrier. opposi ng-directional channe l-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier. 7 cm h is the maximum common-mode voltage slew rate that can be sustained while maintaining v o > 0.8 v dd2 . cm l is the maximum common-mod e voltage slew rate that can be sustained while maintaining v o < 0.8 v. the common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. the transient magnitude is the range over which the common mode is slewed. 8 dynamic supply current is the incremental amou nt of supply current required for a 1 mbps increase in signal data rate. see through for information on per-channel supply current for unloaded and loaded conditions. see the section for guidance on calculating the per-channel supply current for a given data rate. adum1300/adum1301 rev. h | page 13 of 28 electrical characteristics3 v, 125c operation all voltages are relative to their respective ground. 3.0 v v dd1 3.6 v, 3.0 v v dd2 3.6 v; all minimum/maximum specifications apply over the entire recommended operation range, unless otherwise noted; all typical specifications are at t a = 25c, v dd1 = v dd2 = 3.0 v. these specifications apply to adum1300w and adum1301w automotive grade versions. table 5. parameter symbol min typ max unit test conditions dc specifications input supply current per channel, quiescent i ddi (q) 0.26 0.31 ma output supply current pe r channel, quiescent i ddo (q) 0.11 0.15 ma adum1300w, total supply current, three channels 1 dc to 2 mbps v dd1 supply current i dd1 (q) 0.9 1.7 ma dc to 1 mhz logic signal freq. v dd2 supply current i dd2 (q) 0.4 0.7 ma dc to 1 mhz logic signal freq. 10 mbps (trwz grade only) v dd1 supply current i dd1 (10) 3.4 4.9 ma 5 mhz logic signal freq. v dd2 supply current i dd2 (10) 1.1 1.6 ma 5 mhz logic signal freq. adum1301w, total supply current, three channels 1 dc to 2 mbps v dd1 supply current i dd1 (q) 0.7 1.4 ma dc to 1 mhz logic signal freq. v dd2 supply current i dd2 (q) 0.6 0.9 ma dc to 1 mhz logic signal freq. 10 mbps (trwz grade only) v dd1 supply current i dd1 (10) 2.6 3.7 ma 5 mhz logic signal freq. v dd2 supply current i dd2 (10) 1.8 2.5 ma 5 mhz logic signal freq. for all models input currents i ia , i ib , i ic , i e1 , i e2 ?10 +0.01 +10 a 0 v ia , v ib , v ic v dd1 or v dd2 , 0 v e1 ,v e2 v dd1 or v dd2 logic high input threshold v ih , v eh 1.6 v logic low input threshold v il , v el 0.4 v logic high output voltages v oah , v obh , v och v dd1 , v dd2 ? 0.1 3.0 v i ox = ?20 a, v ix = v ixh v dd1 , v dd2 ? 0.4 2.8 v i ox = ?4 ma, v ix = v ixh logic low output voltages v oal , v obl , v ocl 0.0 0.1 v i ox = 20 a, v ix = v ixl 0.04 0.1 v i ox = 400 a, v ix = v ixl 0.2 0.4 v i ox = 4 ma, v ix = v ixl switching specifications adum130xwsrwz minimum pulse width 2 pw 1000 ns c l = 15 pf, cmos signal levels maximum data rate 3 1 mbps c l = 15 pf, cmos signal levels propagation delay 4 t phl , t plh 50 75 100 ns c l = 15 pf, cmos signal levels pulse width distortion, |t plh ? t phl | 4 pwd 40 ns c l = 15 pf, cmos signal levels propagation delay skew 5 t psk 50 ns c l = 15 pf, cmos signal levels channel-to-channel matching 6 t pskcd /t pskod 50 ns c l = 15 pf, cmos signal levels adum130xwtrwz minimum pulse width 2 pw 100 ns c l = 15 pf, cmos signal levels maximum data rate 3 10 mbps c l = 15 pf, cmos signal levels propagation delay 4 t phl , t plh 20 34 45 ns c l = 15 pf, cmos signal levels pulse width distortion, |t plh ? t phl | 4 pwd 3 ns c l = 15 pf, cmos signal levels change vs. temperature 5 ps/c c l = 15 pf, cmos signal levels propagation delay skew 5 t psk 26 ns c l = 15 pf, cmos signal levels channel-to-channel matching, codirectional channels 6 t pskcd 3 ns c l = 15 pf, cmos signal levels channel-to-channel matching, opposing-directional channels 6 t pskod 6 ns c l = 15 pf, cmos signal levels adum1300/adum1301 rev. h | page 14 of 28 parameter symbol min typ max unit test conditions for all models output disable propagation delay (high/low to high impedance) t phz , t plh 6 8 ns c l = 15 pf, cmos signal levels output enable propagation delay (high impedance to high/low) t pzh , t pzl 6 8 ns c l = 15 pf, cmos signal levels output rise/fall time (10% to 90%) t r /t f 3 ns c l = 15 pf, cmos signal levels common-mode transient immunity at logic high output 7 |cm h | 25 35 kv/s v ix = v dd1 /v dd2 , v cm = 1000 v, transient magnitude = 800 v common-mode transient immunity at logic low output 7 |cm l | 25 35 kv/s v ix = 0 v, v cm = 1000 v, transient magnitude = 800 v refresh rate f r 1.1 mbps input dynamic supply current per channel 8 i ddi (d) 0.10 ma/mbps output dynamic supply current per channel 8 i ddo (d) 0.03 ma/mbps 1 the supply current values are for all three channels combined when runni ng at identical data rate s. output supply current valu es are specified with no output load present. the supply current associat ed with an individual channel op erating at a given data rate may be calculated as described in the section. see through for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. see f through for total v dd1 and v dd2 supply currents as a function of data rate for adum1300w/adum1301w ch annel configurations. power consumption power consumption figure 6 fig ure 6 figure 8 figure 8 igure 9 figure 12 2 the minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed. 3 the maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed. 4 t phl propagation delay is measured from the 50% level of the falling edge of the v ix signal to the 50% level of the falling edge of the v ox signal. t plh propagation delay is measured from the 50% level of the rising edge of the v ix signal to the 50% level of the rising edge of the v ox signal. 5 t psk is the magnitude of the worst-case difference in t phl or t plh that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. 6 codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channe ls with inputs on the same side of the isolation barrier. opposi ng-directional channe l-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier. 7 cm h is the maximum common-mode voltage slew rate that can be sustained while maintaining v o > 0.8 v dd2 . cm l is the maximum common-mod e voltage slew rate that can be sustained while maintaining v o < 0.8 v. the common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. the transient magnitude is the range over which the common mode is slewed. 8 dynamic supply current is the incremental amou nt of supply current required for a 1 mbps increase in signal data rate. see through for information on per-channel supply current for unloaded and loaded conditions. see the section for guidance on calculating the per-channel supply current for a given data rate. adum1300/adum1301 rev. h | page 15 of 28 electrical characteristicsmixed 5 v/3 v, 125c operation 1 all voltages are relative to their respective ground. 4.5 v v dd1 5.5 v, 3.0 v v dd2 3.6 v; all minimum/maximum specifications apply over the entire recommended operation range, unless otherwise noted; all typical specifications are at t a = 25c; v dd1 = 5 v, v dd2 = 3.0 v. these specifications apply to adum1300w and adum1301w automotive grade versions. table 6. parameter symbol min typ max unit test conditions dc specifications input supply current per channel, quiescent i ddi (q) 0.50 0.53 ma output supply current per channel, quiescent i ddo (q) 0.11 0.15 ma adum1300w, total supply current, three channels 2 dc to 2 mbps v dd1 supply current i dd1 (q) 1.6 2.5 ma dc to 1 mhz logic signal freq. v dd2 supply current i dd2(q) 0.4 0.7 ma dc to 1 mhz logic signal freq. 10 mbps (trwz grade only) v dd1 supply current i dd1 (10) 6.5 8.1 ma 5 mhz logic signal freq. v dd2 supply current i dd2 (10) 1.1 1.6 ma 5 mhz logic signal freq. adum1301w, total supply current, three channels 1 dc to 2 mbps v dd1 supply current i dd1 (q) 1.3 2.1 ma dc to 1 mhz logic signal freq. v dd2 supply current i dd2 (q) 0.6 0.9 ma dc to 1 mhz logic signal freq. 10 mbps (trwz grade only) v dd1 supply current i dd1 (10) 5.0 6.2 ma 5 mhz logic signal freq. v dd2 supply current i dd2 (10) 1.8 2.5 ma 5 mhz logic signal freq. for all models input currents i ia , i ib , i ic , i e1 , i e2 ?10 +0.01 +10 a 0 v ia ,v ib , v ic v dd1 or v dd2 , 0 v e1 ,v e2 v dd1 or v dd2 logic high input threshold v ih , v eh 2.0 v logic low input threshold v il , v el 0.8 v logic high output voltages v oah , v obh , v och v dd1 , v dd2 ? 0.1 v dd1 , v dd2 v i ox = ?20 a, v ix = v ixh v dd1 , v dd2 ? 0.4 v dd1 , v dd2 ? 0.2 v i ox = ?4 ma, v ix = v ixh logic low output voltages v oal , v obl , v ocl 0.0 0.1 v i ox = 20 a, v ix = v ixl 0.04 0.1 v i ox = 400 a, v ix = v ixl 0.2 0.4 v i ox = 4 ma, v ix = v ixl switching specifications adum130xwsrwz minimum pulse width 3 pw 1000 ns c l = 15 pf, cmos signal levels maximum data rate 4 1 mbps c l = 15 pf, cmos signal levels propagation delay 5 t phl , t plh 50 70 100 ns c l = 15 pf, cmos signal levels pulse width distortion, |t plh ? t phl | 4 pwd 40 ns c l = 15 pf, cmos signal levels propagation delay skew 6 t psk 50 ns c l = 15 pf, cmos signal levels channel-to-channel matching 7 t pskcd /t pskod 50 ns c l = 15 pf, cmos signal levels adum130xwtrwz minimum pulse width 2 pw 100 ns c l = 15 pf, cmos signal levels maximum data rate 3 10 mbps c l = 15 pf, cmos signal levels propagation delay 4 t phl , t plh 20 30 40 ns c l = 15 pf, cmos signal levels pulse width distortion, |t plh ? t phl | 4 pwd 3 ns c l = 15 pf, cmos signal levels change vs. temperature 5 ps/c c l = 15 pf, cmos signal levels propagation delay skew 5 t psk 6 ns c l = 15 pf, cmos signal levels channel-to-channel matching, codirectional channels 6 t pskcd 3 ns c l = 15 pf, cmos signal levels channel-to-channel matching, opposing- directional channels 6 t pskod 22 ns c l = 15 pf, cmos signal levels adum1300/adum1301 rev. h | page 16 of 28 parameter symbol min typ max unit test conditions for all models output disable propagation delay (high/low to high impedance) t phz , t plh 6 8 ns c l = 15 pf, cmos signal levels output enable propagation delay (high impedance to high/low) t pzh , t pzl 6 8 ns c l = 15 pf, cmos signal levels output rise/fall time (10% to 90%) t r /t f 3.0 ns c l = 15 pf, cmos signal levels common-mode transient immunity at logic high output 8 |cm h | 25 35 kv/s v ix = v dd1 /v dd2 , v cm = 1000 v, transient magnitude = 800 v common-mode transient immunity at logic low output 7 |cm l | 25 35 kv/s v ix = 0 v, v cm = 1000 v, transient magnitude = 800 v refresh rate f r 1.2 mbps input dynamic supply current per channel 9 i ddi (d) 0.19 ma/mbps output dynamic supply current per channel 8 i ddo (d) 0.03 ma/mbps 1 all voltages are relative to their respective ground. 2 the supply current values are for all three channels combined when running at identical data rates. output supply current valu es are specified with no output load present. the supply current associated with an individual channel operating at a given data rate may be calculated as described in the section. see through for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. see through for total v dd1 and v dd2 supply currents as a function of data rate for adum1300w/adum1301w channel configurations. power consumption ower consumption figure 6 g ure 6 figure 8 figure 8 figur e 9 figure 12 3 the minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed. 4 the maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed. 5 t phl propagation delay is measured from the 50% level of the falling edge of the v ix signal to the 50% level of the falling edge of the v ox signal. t plh propagation delay is measured from the 50% level of the rising edge of the v ix signal to the 50% level of the rising edge of the v ox signal. 6 t psk is the magnitude of the worst-case difference in t phl or t plh that is measured between units at the same operating temperature, supply voltages , and output load within the recommended operating conditions. 7 codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channe ls with inputs on the same side of the isolation barrier. opposing-directional channel-to-channel matching is the ab solute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier. 8 cm h is the maximum common-mode voltage slew rate that can be sustained while maintaining v o > 0.8 v dd2 . cm l is the maximum common-mode voltage slew rate that can be sustained while maintaining v o < 0.8 v. the common-mode voltage slew rates apply to both rising and falling common-mode voltag e edges. the transient magnitud e is the range over which the common mode is slewed. 9 dynamic supply current is the incremental am ount of supply current required for a 1 mbps increase in signal data rate. see fi through for information on per-channel supply current for unloaded and loaded conditions. see the p section for guidance on calculating th e per-channel supply current for a given data rate. adum1300/adum1301 rev. h | page 17 of 28 electrical characteristicsmixed 3 v/5 v operation all voltages are relative to their respective ground. 3.0 v v dd1 3.6 v, 4.5 v v dd2 5.5 v; all minimum/maximum specifications apply over the entire recommended operation range, unless otherwise noted; all typical specifications are at t a = 25c; v dd1 = 3.0 v, v dd2 = 5 v. these apply to adum1300w and adum1301w automotive grade versions. table 7. parameter symbol min typ max unit test conditions dc specifications input supply current per channel, quiescent i ddi (q) 0.26 0.31 ma output supply current per channel, quiescent i ddo (q) 0.19 0.24 ma adum1300w, total supply current, three channels 1 dc to 2 mbps v dd1 supply current i dd1 (q) 0.9 1.7 ma dc to 1 mhz logic signal freq. v dd2 supply current i dd2(q) 0.7 1.0 ma dc to 1 mhz logic signal freq. 10 mbps (trwz grade only) v dd1 supply current i dd1 (10) 3.4 4.9 ma 5 mhz logic signal freq. v dd2 supply current i dd2 (10) 1.9 2.5 ma 5 mhz logic signal freq. adum1301w, total supply current, three channels 1 dc to 2 mbps v dd1 supply current i dd1 (q) 0.7 1.4 ma dc to 1 mhz logic signal freq. v dd2 supply current i dd2 (q) 1.0 1.4 ma dc to 1 mhz logic signal freq. 10 mbps (trwz grade only) v dd1 supply current i dd1 (10) 2.6 3.7 ma 5 mhz logic signal freq. v dd2 supply current i dd2 (10) 3.4 4.2 ma 5 mhz logic signal freq. for all models input currents i ia , i ib , i ic , i e1 , i e2 ?10 +0.01 +10 a 0 v ia ,v ib , v ic v dd1 or v dd2 , 0 v e1 ,v e2 v dd1 or v dd2 logic high input threshold v ih , v eh 1.6 v logic low input threshold v il , v el 0.4 v logic high output voltages v oah , v obh , v och v dd1 , v dd2 ? 0.1 v dd1 , v dd2 v i ox = ?20 a, v ix = v ixh v dd1 , v dd2 ? 0.4 v dd1 , v dd2 ? 0.2 v i ox = ?4 ma, v ix = v ixh logic low output voltages v oal , v obl , v ocl 0.0 0.1 v i ox = 20 a, v ix = v ixl 0.04 0.1 v i ox = 400 a, v ix = v ixl 0.2 0.4 v i ox = 4 ma, v ix = v ixl switching specifications adum130xwsrwz minimum pulse width 2 pw 1000 ns c l = 15 pf, cmos signal levels maximum data rate 3 1 mbps c l = 15 pf, cmos signal levels propagation delay 4 t phl , t plh 50 70 100 ns c l = 15 pf, cmos signal levels pulse width distortion, |t plh ? t phl | 4 pwd 40 ns c l = 15 pf, cmos signal levels propagation delay skew 5 t psk 50 ns c l = 15 pf, cmos signal levels channel-to-channel matching 6 t pskcd /t pskod 50 ns c l = 15 pf, cmos signal levels adum130xwtrwz minimum pulse width 2 pw 100 ns c l = 15 pf, cmos signal levels maximum data rate 3 10 mbps c l = 15 pf, cmos signal levels propagation delay 4 t phl , t plh 20 30 40 ns c l = 15 pf, cmos signal levels pulse width distortion, |t plh ? t phl | 4 pwd 3 ns c l = 15 pf, cmos signal levels change vs. temperature 5 ps/c c l = 15 pf, cmos signal levels propagation delay skew 5 t psk 6 ns c l = 15 pf, cmos signal levels channel-to-channel matching, codirectional channels 6 t pskcd 3 ns c l = 15 pf, cmos signal levels channel-to-channel matching, opposing- directional channels 6 t pskod 22 ns c l = 15 pf, cmos signal levels adum1300/adum1301 rev. h | page 18 of 28 parameter symbol min typ max unit test conditions for all models output disable propagation delay (high/low to high impedance) t phz , t plh 6 8 ns c l = 15 pf, cmos signal levels output enable propagation delay (high impedance to high/low) t pzh , t pzl 6 8 ns c l = 15 pf, cmos signal levels output rise/fall time (10% to 90%) t r /t f c l = 15 pf, cmos signal levels 5 v/3 v operation 3.0 ns 3 v/5 v operation 2.5 ns common-mode transient immunity at logic high output 7 |cm h | 25 35 kv/s v ix = v dd1 /v dd2 , v cm = 1000 v, transient magnitude = 800 v common-mode transient immunity at logic low output 7 |cm l | 25 35 kv/s v ix = 0 v, v cm = 1000 v, transient magnitude = 800 v refresh rate f r 1.1 mbps input dynamic supply current per channel 8 i ddi (d) 0.10 ma/mbps output dynamic supply current per channel 8 i ddo (d) 0.05 ma/mbps 1 the supply current values are for all three channels combined when running at identical data rates. output supply current valu es are specified with no output load present. the supply current associated with an individual channel operating at a given data rate may be calculated as described in the power consumption section. see figure 6 through figure 8 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. see figur e 9 through figure 12 for total v dd1 and v dd2 supply currents as a function of data rate for adum1300w/adum1301w channel configurations. 2 the minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed. 3 the maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed. 4 t phl propagation delay is measured from the 50% level of the falling edge of the v ix signal to the 50% level of the falling edge of the v ox signal. t plh propagation delay is measured from the 50% level of the rising edge of the v ix signal to the 50% level of the rising edge of the v ox signal. 5 t psk is the magnitude of the worst-case difference in t phl or t plh that is measured between units at the same operating temperature, supply voltages , and output load within the recommended operating conditions. 6 codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channe ls with inputs on the same side of the isolation barrier. opposing-directional channel-to-channel matching is the ab solute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier. 7 cm h is the maximum common-mode voltage slew rate that can be sustained while maintaining v o > 0.8 v dd2 . cm l is the maximum common-mode voltage slew rate that can be sustained while maintaining v o < 0.8 v. the common-mode voltage slew rates apply to both rising and falling common-mode voltag e edges. the transient magnitud e is the range over which the common mode is slewed. 8 dynamic supply current is the incremental am ount of supply current required for a 1 mbps increase in signal data rate. see fig ure 6 through figure 8 for information on per-channel supply current for unloaded and loaded conditions. see the power consumption section for guidance on calculating th e per-channel supply current for a given data rate. adum1300/adum1301 rev. h | page 19 of 28 package characteristics table 8. parameter symbol min typ max unit test conditions resistance (input-to-output) 1 r i-o 10 12 capacitance (input-to-output) 1 c i-o 1.7 pf f = 1 mhz input capacitance 2 c i 4.0 pf ic junction-to-case thermal resistance, side 1 jci 33 c/w thermocouple located at center of package underside ic junction-to-case thermal resistance, side 2 jco 28 c/w 1 device is considered a 2-terminal device; pin 1, pin 2, pin 3, pin 4, pin 5, pin 6, pin 7, and pin 8 are shorted together and pin 9, pin 10, pin 11, pin 12, pin 13, pin 14, pin 15, and pin 16 are shorted together. 2 input capacitance is from any input data pin to ground. regulatory information the adum130x are approved by the organizations listed in table 9. refer to table 14 and the insulation lifetime section for details regarding recommended maximum working voltages for specific crossisolation waveforms and insulation levels. table 9. ul csa vde tv recognized under 1577 component recognition program 1 approved under csa component acceptance notice #5a certified according to din v vde v 0884-10 (vde v 0884-10):2006-12 2 approved according to: iec 61010-1:2001 (2 nd edition), en 61010-1:2001 (2 nd edition), ul 61010-1:2004 csa c22.2.61010.1:2005 double/reinforced insulation, 2500 v rms isolation voltage basic insulation per csa 60950-1-03 and iec 60950-1, 800 v rms (1131 v peak) maximum working voltage reinforced insulation per csa 60950-1-03 and iec 60950-1, 400 v rms (566 v peak) maximum working voltage reinforced insulation, 560 v peak reinforced insulation, 400 v rms maximum working voltage file e214100 file 205078 file 2471900-4880-0001 certificate u8v 05 06 56232 002 1 in accordance with ul 1577, each adum130x is proof tested by a pplying an insulation test voltage 3000 v rms for 1 sec (curren t leakage detection limit = 5 a). 2 in accordance with din v vde v 0884-10, each adum130x is pr oof tested by applying an insulati on test voltage 1050 v peak for 1 sec (partial discharge detection limit = 5 pc). the * marking branded on the component designates din v vde v 0884-10 approval. insulation and safety-related specifications table 10. parameter symbol value unit conditions rated dielectric insulation voltage 2500 v rms 1-minute duration minimum external air gap (clearance) l(i01) 7.7 min mm measured from input termin als to output terminals, shortest distance through air minimum external tracking (creepage) l(i02) 8.1 min mm measured from input termin als to output terminals, shortest distance path along body minimum internal gap (internal clearance) 0.017 min mm insulation distance through insulation tracking resistance (comparative tracking index) cti >175 v din iec 112/vde 0303 part 1 isolation group iiia material group (din vde 0110, 1/89, table 1) adum1300/adum1301 rev. h | page 20 of 28 din v vde v 0884-10 (vde v 0884-10):2006- 12 insulation characteristics these isolators are suitable for reinforced electrical isolation only within the safety limit data. maintenance of the safety d ata is ensured by protective circuits. the * marking on packages denotes din v vde v 0884-10 approval for 560 v peak working voltage. table 11. description conditions symbol characteristic unit installation classification per din vde 0110 for rated mains voltage 150 v rms i to iv for rated mains voltage 300 v rms i to iii for rated mains voltage 400 v rms i to ii climatic classification 40/105/21 pollution degree per din vde 0110, table 1 2 maximum working insulation voltage v iorm 560 v peak input-to-output test voltage, method b1 v iorm 1.875 = v pr , 100% production test, t m = 1 sec, partial discharge < 5 pc v pr 1050 v peak input-to-output test voltage, method a v iorm 1.6 = v pr , t m = 60 sec, partial discharge < 5 pc v pr after environmental tests subgroup 1 896 v peak after input and/or safety test subgroup 2 and subgroup 3 v iorm 1.2 = v pr , t m = 60 sec, partial discharge < 5 pc 672 v peak highest allowable overvoltage transient overvoltage, t tr = 10 seconds v tr 4000 v peak safety-limiting values maximum value allowed in the event of a failure (see figure 3 ) case temperature t s 150 c side 1 current i s1 265 ma side 2 current i s2 335 ma insulation resistance at t s v io = 500 v r s >10 9 case temperature (c) safety-limiting current (ma) 0 0 350 300 250 200 150 100 50 50 100 150 200 side #1 side #2 03787-003 figure 3. thermal derating curve, dependence of safety-limiting values with case temperature per din v vde v 0884-10 recommended operat ing conditions table 12. parameter rating operating temperature (t a ) 1 ?40c to +105c operating temperature (t a ) 2 ?40c to +125c supply voltages (v dd1 , v dd2 ) 1 , 3 2.7 v to 5.5 v supply voltages (v dd1 , v dd2 ) 2 , 3 3.0 v to 5.5 v input signal rise and fall times 1.0 ms 1 does not apply to adum1300w and adum1301w automotive grade versions. 2 applies to adum1300w and adum1301w automoti ve grade versions. 3 all voltages are relative to their respective ground. see the section fo r information on immu nity to external magnetic fields. dc correctness and magnetic field immunity adum1300/adum1301 rev. h | page 21 of 28 absolute maximum ratings ambient temperature = 25c, unless otherwise noted. table 13. parameter rating storage temperature (t st ) ?65c to +150c ambient operating temperature (t a ) 1 ?40c to +105c ambient operating temperature (t a ) 2 ?40c to +125c supply voltages (v dd1 , v dd2 ) 3 ?0.5 v to +7.0 v input voltage (v ia , v ib , v ic , v e1 , v e2 ) 3, 4 ?0.5 v to v ddi + 0.5 v output voltage (v oa , v ob , v oc ) 3, 4 ?0.5 v to v ddo + 0.5 v average output current per pin 5 side 1 (i o1 ) ?23 ma to +23 ma side 2 (i o2 ) ?30 ma to +30 ma common-mode transients 6 ?100 kv/s to +100 kv/s 1 does not apply to adum1300w and adum1301w automotive grade versions. 2 applies to adum1300w and adum 1301w automotive grade versions. 3 all voltages are relative to their respective ground. 4 v ddi and v ddo refer to the supply voltages on the input and output sides of a given channel, respectively. see the pc board layout section. 5 see figure 3 for maximum rated current values for various temperatures. 6 this refers to common-mode transients across the insulation barrier. common-mode transients exceeding the absolute maximum ratings may cause latch-up or permanent damage. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution table 14. maximum continuous working voltage 1 parameter max unit constraint ac voltage, bipolar waveform 565 v peak 50-year minimum lifetime ac voltage, unipolar waveform basic insulation 1131 v peak maximum ap proved working voltage per iec 60950-1 reinforced insulation 560 v peak maximum approved working voltage per iec 60950-1 and vde v 0884-10 dc voltage basic insulation 1131 v peak maximum ap proved working voltage per iec 60950-1 reinforced insulation 560 v peak maximum approved working voltage per iec 60950-1 and vde v 0884-10 1 refers to continuous voltage magnitude imposed across the isol ation barrier. see the section for more deta ils. insulation lifetime table 15. truth table (positive logic) v ix input 1 v ex input 1 , 2 v ddi state 1 v ddo state 1 v ox output 1 notes h h or nc powered powered h l h or nc powered powered l x l powered powered z x h or nc unpowered powered h outputs retur n to the input state within 1 s of v ddi power restoration. x l unpowered powered z x x powered unpowered indeterminate outputs return to the input state within 1 s of v ddo power restoration, if the v ex state is h or nc. outputs returns to a high impedance state within 8 ns of v ddo power restoration, if the v ex state is l. 1 v ix and v ox refer to the input and output signals of a given channel (a, b, or c). v ex refers to the output enable signal on the same side as the v ox outputs. v ddi and v ddo refer to the supply voltages on the input and output sides of the given channel, respectively. 2 in noisy environments, connecting v ex to an external logic hi gh or low is recommended. adum1300/adum1301 rev. h | page 22 of 28 pin configurations and function descriptions v dd1 1 *gnd 1 2 v ia 3 v ib 4 v dd2 16 gnd 2 * 15 v oa 14 v ob 13 v ic 5 v oc 12 nc 6 nc 11 nc 7 v e2 10 *gnd 1 8 gnd 2 * 9 nc = no connect adum1300 top view (not to scale) 03787-004 * pin 2 and pin 8 are internally connected, and connecting both to gnd 1 is recommended. pin 9 and pin 15 are internally connected, and connecting both to gnd 2 is recommended. 03787-005 v dd1 1 *gnd 1 2 v ia 3 v ib 4 v dd2 16 gnd 2 * 15 v oa 14 v ob 13 v oc 5 v ic 12 nc 6 nc 11 v e1 7 v e2 10 *gnd 1 8 gnd 2 * 9 nc = no connect adum1301 top view (not to scale) *pin 2 and pin 8 are internally connected, and connecting both to gnd 1 is recommended. pin 9 and pin 15 are internally connected, and connecting both to gnd 2 is recommended. figure 4. adum1300 pin configuration figure 5. adum1301 pin configuration table 16. adum1300 pin function descriptions pin no. mnemonic description 1 v dd1 supply voltage for isolator side 1. 2 gnd 1 ground 1. ground reference for isolator side 1. 3 v ia logic input a. 4 v ib logic input b. 5 v ic logic input c. 6 nc no connect. 7 nc no connect. 8 gnd 1 ground 1. ground reference for isolator side 1. 9 gnd 2 ground 2. ground reference for isolator side 2. 10 v e2 output enable 2. active high logic input. v oa , v ob , and v oc outputs are enabled when v e2 is high or disconnected. v oa , v ob , and v oc outputs are disabled when v e2 is low. in noisy environments, connecting v e2 to an external logic hi gh or low is recommended. 11 nc no connect. 12 v oc logic output c. 13 v ob logic output b. 14 v oa logic output a. 15 gnd 2 ground 2. ground reference for isolator side 2. 16 v dd2 supply voltage for isolator side 2. table 17. adum1301 pin function descriptions pin no. mnemonic description 1 v dd1 supply voltage for isolator side 1. 2 gnd 1 ground 1. ground reference for isolator side 1. 3 v ia logic input a. 4 v ib logic input b. 5 v oc logic output c. 6 nc no connect. 7 v e1 output enable 1. active high logic input. v oc output is enabled when v e1 is high or disconnected. v oc is disabled when v e1 is low. in noisy environments, connecting v e1 to an external logic high or low is recommended. 8 gnd 1 ground 1. ground reference for isolator side 1. 9 gnd 2 ground 2. ground reference for isolator side 2. 10 v e2 output enable 2. active high logic input. v oa and v ob outputs are enabled when v e2 is high or discon- nected. v oa and v ob outputs are disabled when v e2 is low. in noisy environments, connectingv e2 to an external logic high or low is recommended. 11 nc no connect. 12 v ic logic input c. 13 v ob logic output b. 14 v oa logic output a. 15 gnd 2 ground 2. ground reference for isolator side 2. 16 v dd2 supply voltage for isolator side 2. adum1300/adum1301 rev. h | page 23 of 28 typical performance characteristics data rate (mbps) current/channel (ma) 0 0 6 4 2 14 12 10 8 16 18 20 40 20 60 80 100 5v 3v 03787-008 figure 6. typical input supply current per channel vs. data rate for 5 v and 3 v operation data rate (mbps) current/channel (ma) 0 0 2 4 3 5 1 6 20 40 60 80 100 5v 3v 03787-009 figure 7. typical output supply current per channel vs. data rate for 5 v and 3 v operation (no output load) data rate (mbps) current/channel (ma) 0 0 10 9 8 7 6 5 4 3 2 1 20 40 80 60 100 5v 3v 03787-010 figure 8. typical output supply current per channel vs. data rate for 5 v and 3 v operation (15 pf output load) data rate (mbps) current (ma) 02 0 0 20 10 50 40 30 60 40 60 80 100 5v 3v 03787-011 figure 9. typical adum1300 v dd1 supply current vs. data rate for 5 v and 3 v operation data rate (mbps) current (ma) 0 0 4 2 10 8 6 12 16 14 40 20 60 80 100 5v 3v 03787-012 figure 10. typical adum1300 v dd2 supply current vs. data rate for 5 v and 3 v operation data rate (mbps) current (ma) 0 0 15 10 5 45 40 35 30 25 20 50 20 40 60 80 100 5v 3v 03787-013 figure 11. typical adum1301 v dd1 supply current vs. data rate for 5 v and 3 v operation adum1300/adum1301 rev. h | page 24 of 28 data rate (mbps) current (ma) 0 0 10 5 20 15 25 30 20 40 60 80 100 5v 3v 03787-014 figure 12. typical adum1301 v dd2 supply current vs. data rate for 5 v and 3 v operation temperature (c) propagation delay (ns) ?50 ?25 25 30 35 40 05 0 7 5 25 100 3v 5v 03787-019 figure 13. propagation delay vs. temperature, c grade adum1300/adum1301 rev. h | page 25 of 28 applications information pc board layout the adum130x digital isolator requires no external interface circuitry for the logic interfaces. power supply bypassing is strongly recommended at the input and output supply pins (see figure 14 ). bypass capacitors are most conveniently connected between pin 1 and pin 2 for v dd1 and between pin 15 and pin 16 for v dd2 . the capacitor value should be between 0.01 f and 0.1 f. the total lead length between both ends of the capacitor and the input power supply pin should not exceed 20 mm. bypassing between pin 1 and pin 8 and between pin 9 and pin 16 should also be considered unless the ground pair on each package side is connected close to the package. v dd1 gnd 1 v ia v ib v ic/ v oc nc nc/v e1 gnd 1 v dd2 gnd 2 v oa v ob v oc/ v ic nc v e2 gnd 2 0 3787-015 figure 14. recommended printed circuit board layout in applications involving high common-mode transients, care should be taken to ensure that board coupling across the isolation barrier is minimized. furthermore, the board layout should be designed such that any coupling that does occur equally affects all pins on a given component side. failure to ensure this could cause voltage differentials between pins exceeding the absolute maximum ratings of the device, thereby leading to latch-up or permanent damage. propagation delay-related parameters propagation delay is a parameter that describes the time it takes a logic signal to propagate through a component. the propagation delay to a logic low output may differ from the propagation delay to a logic high output. input ( v ix ) output (v ox ) t plh t phl 50% 50% 0 3787-016 figure 15. propagation delay parameters pulse width distortion is the maximum difference between these two propagation delay values and is an indication of how accurately the timing of the input signal is preserved. channel-to-channel matching refers to the maximum amount that the propagation delay differs between channels within a single adum130x component. propagation delay skew refers to the maximum amount that the propagation delay differ s between multiple adum130x components operating under the same conditions. dc correctness and magnetic field immunity positive and negative logic transitions at the isolator input cause narrow (~1 ns) pulses to be sent to the decoder via the transformer. the decoder is bistable and is therefore either set or reset by the pulses, indicating input logic transitions. in the absence of logic transitions at the input for more than ~1 s, a periodic set of refresh pulses indicative of the correct input state are sent to ensure dc correctness at the output. if the decoder receives no internal pulses for more than about 5 s, the input side is assumed to be unpowered or nonfunctional, in which case the isolator output is forced to a default state (see table 1 5 ) by the watchdog timer circuit. the adum130x is extremely immune to external magnetic fields. the limitation on the magnetic field immunity of the adum130x is set by the condition in which induced voltage in the receiving coil of the transformer is sufficiently large enough to either falsely set or reset the decoder. the following analysis defines the conditions under which this may occur. the 3 v operating condition of the adum130x is examined because it represents the most susceptible mode of operation. the pulses at the transformer output have an amplitude greater than 1.0 v. the decoder has a sensing threshold at about 0.5 v, thus establishing a 0.5 v margin in which induced voltages can be tolerated. the voltage induced across the receiving coil is given by v = ( ? d /dt )? r n 2 ; n = 1, 2, , n where: is magnetic flux density (gauss). n is the number of turns in the receiving coil. r n is the radius of the n th turn in the receiving coil (cm). given the geometry of the receiving coil in the adum130x and an imposed requirement that the induced voltage be 50% at most of the 0.5 v margin at the decoder, a maximum allowable magnetic field is calculated as shown in figure 16 . magnetic field frequency (hz) 100 maximum allowable magnetic flux density (kgauss) 0.001 1m 10 0.01 1k 10k 10m 0.1 1 100m 100k 0 3787-017 figure 16. maximum allowable external magnetic flux density adum1300/adum1301 rev. h | page 26 of 28 for example, at a magnetic field frequency of 1 mhz, the maximum allowable magnetic field of 0.2 kgauss induces a voltage of 0.25 v at the receiving coil. this is about 50% of the sensing threshold and does not cause a faulty output transition. similarly, if such an event occurs during a transmitted pulse (and has the worst-case polarity), it reduces the received pulse from >1.0 v to 0.75 vstill well above the 0.5 v sensing threshold of the decoder. the preceding magnetic flux density values correspond to specific current magnitudes at given distances from the adum130x transformers. figure 17 shows these allowable current magnitudes as a function of frequency for selected distances. the adum130x is extremely immune and can be affected only by extremely large currents operated at a high frequency very close to the component. for the 1 mhz example noted, one would have to place a 0.5 ka current 5 mm away from the adum130x to affect the operation of the component. magnetic field frequency (hz) maximum allowable current (ka) 1000 100 10 1 0.1 0.01 1k 10k 100m 100k 1m 10m distance = 5mm distance = 1m distance = 100mm 03787-018 figure 17. maximum allowable current for various current-to-adum130x spacings note that at combinations of strong magnetic field and high frequency, any loops formed by printed circuit board traces could induce error voltages sufficiently large enough to trigger the thresholds of succeeding circuitry. care should be taken in the layout of such traces to avoid this possibility. power consumption the supply current at a given channel of the adum130x isolator is a function of the supply voltage, the data rate of the channel, and the output load of the channel. for each input channel, the supply current is given by i ddi = i ddi ( q ) f 0.5 f r i ddi = i ddi ( d ) (2 f ? f r ) + i ddi (q) f > 0.5 f r for each output channel, the supply current is given by i ddo = i ddo ( q ) f 0.5 f r i ddo = ( i ddo ( d ) + (0.5 10 ?3 ) c l v ddo ) (2 f ? f r ) + i ddo ( q ) f > 0.5 f r where: i ddi ( d ) , i ddo ( d ) are the input and output dynamic supply currents per channel (ma/mbps). c l is the output load capacitance (pf). v ddo is the output supply voltage (v). f is the input logic signal frequency (mhz); it is half of the input data rate expressed in units of mbps. f r is the input stage refresh rate (mbps). i ddi ( q ) , i ddo ( q ) are the specified input and output quiescent supply currents (ma). to calculate the total v dd1 and v dd2 supply current, the supply currents for each input and output channel corresponding to v dd1 and v dd2 are calculated and totaled. figure 6 and figure 7 provide per-channel supply currents as a function of data rate for an unloaded output condition. figure 8 provides per-channel supply current as a function of data rate for a 15 pf output condition. figure 9 through figure 12 provide total v dd1 and v dd2 supply current as a function of data rate for adum1300/ adum1301 channel configurations. adum1300/adum1301 rev. h | page 27 of 28 insulation lifetime all insulation structures eventually break down when subjected to voltage stress over a sufficiently long period. the rate of insulation degradation is dependent on the characteristics of the voltage waveform applied across the insulation. in addition to the testing performed by the regulatory agencies, analog devices carries out an extensive set of evaluations to determine the lifetime of the insulation structure within the adum130x. analog devices performs accelerated life testing using voltage levels higher than the rated continuous working voltage. accel- eration factors for several operating conditions are determined. these factors allow calculation of the time to failure at the actual working voltage. the values shown in table 14 summarize the peak voltage for 50 years of service life for a bipolar ac operating condition and the maximum csa/vde approved working voltages. in many cases, the approved working voltage is higher than the 50-year service life voltage. operation at these high working voltages can lead to shortened insulation life in some cases. the insulation lifetime of the adum130x depends on the voltage waveform type imposed across the isolation barrier. the i coupler insulation structure degrades at different rates depending on whether the waveform is bipolar ac, unipolar ac, or dc. figure 18 , figure 19 , and figure 20 illustrate these different isolation voltage waveforms, respectively. bipolar ac voltage is the most stringent environment. the goal of a 50-year operating lifetime under the ac bipolar condition determines the analog devices recommended maximum working voltage. in the case of unipolar ac or dc voltage, the stress on the insu- lation is significantly lower, which allows operation at higher working voltages while still achieving a 50-year service life. the working voltages listed in table 14 can be applied while main- taining the 50-year minimum lifetime provided the voltage conforms to either the unipolar ac or dc voltage cases. any cross insulation voltage waveform that does not conform to figure 19 or figure 20 should be treated as a bipolar ac waveform, and its peak voltage should be limited to the 50-year lifetime voltage value listed in table 14 . note that the voltage presented in figure 19 is shown as sinusoidal for illustration purposes only. it is meant to represent any voltage waveform varying between 0 v and some limiting value. the limiting value can be positive or negative, but the voltage cannot cross 0 v. 0v rated peak voltage 03787-021 figure 18. bipolar ac waveform 0v rated peak voltage 03787-022 figure 19. unipolar ac waveform 0v rated peak voltage 03787-023 figure 20. dc waveform automotive products the adum1300w and adum1301w products are qualified per aec-q100 for use in automotive applications. custom variants of these products may be available to meet stringent automotive performance and quality requirements. for more information, contact your local analog devices sales repre- sentative. adum1300/adum1301 rev. h | page 28 of 28 outline dimensions controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design. compliant to jedec standards ms-013- aa 032707-b 10.50 (0.4134) 10.10 (0.3976) 0.30 (0.0118) 0.10 (0.0039) 2.65 (0.1043) 2.35 (0.0925) 10.65 (0.4193) 10.00 (0.3937) 7.60 (0.2992) 7.40 (0.2913) 0 . 7 5 ( 0 . 0 2 9 5 ) 0 . 2 5 ( 0 . 0 0 9 8 ) 45 1.27 (0.0500) 0.40 (0.0157) c oplanarity 0.10 0.33 (0.0130) 0.20 (0.0079) 0.51 (0.0201) 0.31 (0.0122) seating plane 8 0 16 9 8 1 1.27 (0.0500) bsc figure 21. 16-lead standard small outline package [soic_w] wide body (rw-16) dimensions shown in millimeters (and inches) ordering guide model number of inputs, v dd1 side number of inputs, v dd2 side maximum data rate (mbps) maximum propagation delay, 5 v (ns) maximum pulse width distortion (ns) temperature range (c) package option 1 adum1300arw 2 3 0 1 100 40 ?40 to +105 rw-16 adum1300brw 2 3 0 10 50 3 ?40 to +105 rw-16 adum1300crw 2 3 0 90 32 2 ?40 to +105 rw-16 adum1300arwz 2 , 3 3 0 1 100 40 ?40 to +105 rw-16 adum1300brwz 2 , 3 3 0 10 50 3 ?40 to +105 rw-16 adum1300crwz 2 , 3 3 0 90 32 2 ?40 to +105 rw-16 adum1300wsrwz 2 , 3 3 0 1 100 40 ?40 to +125 rw-16 adum1300wtrwz 2 , 3 3 0 10 32 3 ?40 to +125 rw-16 adum1301arw 2 2 1 1 100 40 ?40 to +105 rw-16 adum1301brw 2 2 1 10 50 3 ?40 to +105 rw-16 adum1301crw 2 2 1 90 32 2 ?40 to +105 rw-16 adum1301arwz 2 , 3 2 1 1 100 40 ?40 to +105 rw-16 adum1301brwz 2 , 3 2 1 10 50 3 ?40 to +105 rw-16 adum1301crwz 2 , 3 2 1 90 32 2 ?40 to +105 rw-16 adum1301wsrwz 2 , 3 2 1 1 100 40 ?40 to +125 rw-16 adum1301wtrwz 2 , 3 2 1 10 32 3 ?40 to +125 rw-16 1 rw-16 = 16-lead wide body soic. 2 tape and reel are available. the addition of an -rl suffix designates a 13 (1,000 units) tape-and-reel option. 3 z = rohs compliant part. ?2003C2008 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d03787-0-5/08(h) |
Price & Availability of ADUM1300CRW-RL
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